Buffering and clamping analog signals are important operations in many analog and mixed-signal circuits. One common buffer circuit utilizes a pair of MOS transistors, with one transistor being in the source-follower configuration and the second transistor operating as a current source coupled to the source electrode of the first transistor. This source follower circuit provides a gain of approximately one.
FIG. 1A is another exemplary prior art buffer circuit 6 which provides a more precise gain of one. FIG. 1B shows the output of the buffer circuit 6 connected to the input a circuit 8 which performs further processing of the buffered output. Circuit 8 can perform almost any type of operation on the buffered output, including, by way of example, a line driver circuit, a comparator circuit or the like.
The FIG. 1A circuit 6 includes a pair of NMOS input transistors M1 and M2 which are connected as a differential pair. A tail current source, comprising NMOS transistor M4, is coupled to the common source connections of transistors M1 and M2. A PMOS load transistor M3, which operates in the saturation region, is connected between input transistor M2 and the supply VDD. The output Out of the buffer circuit is at the node intermediate input transistor M2 and load transistor M3. The differential amplifier has a relatively high open loop gain. A direct feedback connection is made from the output back to the inverting input of the differential amplifier, the gate of transistor M2, which sets the gain to be close to one.
In some applications, it is desirable to be able to clamp the output of the buffer circuit so that the output does not exceed some maximum and some minimum predetermined values. The prior art circuit 6 of FIG. 1A does not provide these capabilities. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings, the present invention successfully addresses this shortcoming of the prior art.